LTEQ MICROWAVE

VEGA is a family of Ultra-Fast Converters for 100GbE

Micram VEGA converters are single-chip SiGe solutions with a scalable open architecture for direct conversion between analog and digital domains (ADC & DAC) that allow for sampling rates in excess of 25GS/s. They are built using a library approach that allows for quick adoption of application specific requirements.
The VEGA DAC 25 is a digital to analog converter, a demonstrator IC proving the inherent performance and functional capability of our modular approach (6 bit, operating up to 30 GS/s with an analog bandwidth of 25GHZ). The demonstrator is available on an evaluation board.

Our next converter is the VEGA ADC 30, a 6 bit Analog Digital Converter designed for 30GS/s. Two chips can operate in interleave mode to achieve a sampling rate of 60GS/s at an unseen bandwidth of 20GHz. Further on the roadmap is a single-chip converter chipset for 60GS/s.

VEGA DAC 25 Key Specifications
(product and evaluation board available now)

The scalable open architecture offers a high degree of flexibility in order to adopt the rapidly changing requirements in future high-speed converter applications. Having a physical resolution of 6bits, we measured an ENOB of >5.5bit at 25 GS/s with a sinusoidal differential signal from 0.1 to 6.25 GHz. In the high-speed front end, the VEGA architecture allows a tradeoff between conversion rate, resolution and power consumption for optimum tailored application specific performance. For massive signal and data processing in digital domain, the architecture offers a parallel interface to either commercially available high-speed FPGAs or to a separate custom specific realization in off the shelf standard CMOS technology.

VEGA ADC 30 Target Key Specifications
(product available in 2009)

The ADC 30 is a demonstrator chip for 30GS/s to show the inherent performance and functional capability of the VEGA modular approach. It consists of an input-amplifier, track-and-hold circuit, ADC-core and output logic. The converter has a bandwidth of 20GHz, which shows up when operating two ADCs in interleave mode to provide 60GS/s @ 20 GHz.
Like DAC 25, the first chips will be available with an evaluation board. The ADC chip will be mounted to the PCB board on a chip-carrier (shown here) which allows easy swapping of ADC chips to different (customer) boards.

The conversion will be interleaved, there will be several blocks sharing the conversion operation. Results are processed in a logic block and de-mulitplexed for further processing by external CMOS FPGA chips. The RF-Clock will be fed directly into the A/D converter and will provide a reference clock to the FPGA. Depending on customer needs there may be an option to include a VCO on the chip.

Data-transfer to FPGA will be via 24 serial lines (LVDS or PCML, differential) running at fsample/4, e.g. 7.5Gb/s for 30GS/s (6 bit * 1:4 Mux --> 24 signals). The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and signal input are interfaced by K-connectors.

In addition a register bus (LVTTL, serial) is used to configure and calibrate the A/D converter. Dedicated on-chip circuitry will support for easy calibration.

The high-speed interface will carry raw data only, without line coding (except scrambling) or framing. To compensate for skew on PCB as well as to align input stages in the FPGA, the A/D converter can be switched into a dedicated synchronization mode. Since some FPGA require a certain amount of data edges on the input channels to stay synchronized, the data transmitted to the FPGA can be optionally PRBS scrambled to enforce transitions even while the ADC-input is static.